1.A Low-Power dTLB Design Based on Memory Region Encoding

Xie, JS, Li, XF, Ton     More...

Xie, JS, Li, XF, Tong, D, Chen, J, Cheng, X     Less

CHINESE JOURNAL OF ELECTRONICS[1022-4653], Published 2008, Volume 17, Issue 4, Pages 595-601

收錄情况： WOS SCOPUS

WOS核心合集引用: 0  2023影響因子:  1.6  发表年影響因子:  0.148 

2.Slice Analysis Based Bayesian Power Model for Sequential Circuits

Chen, J, Tong, D, Li     More...

Chen, J, Tong, D, Li, XF, Xie, JS, Wang, KY, Cheng, X     Less

CHINESE JOURNAL OF ELECTRONICS[1022-4653], Published 2010, Volume 19, Issue 1, Pages 107-112

收錄情况： WOS SCOPUS

WOS核心合集引用: 2  2023影響因子:  1.6  发表年影響因子:  0.138